1. Field of the Invention
The present invention relates to a CMOS switch.
2. Description of the Related Art
A switched capacitor circuit is used for a sample hold circuit, an integrator, a switched capacitor filter, and the like. The switched capacitor circuit includes a combination of a capacitor and a complementary metal-oxide semiconductor (CMOS) switch (also referred to as an analog switch or a transfer gate).
FIG. 1A and FIG. 1B are circuit diagrams illustrating a basic configuration of a switched capacitor circuit. A switched capacitor circuit 10r is a sample hold circuit, and includes a hold capacitor COUT and a CMOS switch SW1. An input voltage VIN is applied to one end of the CMOS switch SW1, and the other end thereof is connected to the capacitor COUT. When the CMOS switch SW1 is turned on, the capacitor COUT is charged with the input voltage VIN (sample), and the input voltage VIN is held even after the CMOS switch SW1 is turned off (hold).
As illustrated in FIG. 1B, the CMOS switch SW1 includes an N-channel metal-oxide semiconductor (NMOS) transistor and a P-channel metal-oxide semiconductor (PMOS) transistor connected in parallel.
When a drive circuit 20r makes a clock CK a high level and a complementary clock CKB a low level, the CMOS switch SW1 becomes conductive.
As illustrated in FIG. 1B, the NMOS transistor has parasitic capacitances CNS, CND, and CNB between a gate and a source, between the gate and a drain, and between the gate and a substrate (back gate). Similarly, the PMOS transistor has parasitic capacitances CPS, CPD, and CPB between a gate and a source, between the gate and a drain, and between the gate and a substrate.
FIG. 2 is an operation waveform diagram of the switched capacitor circuit 10r of FIG. 1A and FIG. 1B. When the clock CK is shifted to the high level and the complementary clock CKB is shifted to the low level at time t0, the CMOS switch SW1 is turned on. As a result, the capacitor COUT is charged with the input voltage VIN, and an output voltage VOUT approaches the input voltage VIN. Subsequently, when the clock CK is shifted to the low level and the complementary clock CKB is shifted to the high level at time t1, the CMOS switch SW1 is turned off. At this time, an error ΔVOUT is generated between the output voltage VOUT and the input voltage VIN due to clock feed-through and charge injection caused by the parasitic capacitances.
The clock feed-through is a phenomenon in which a high frequency component included in an edge of a gate signal (clock signal) of a metal-oxide semiconductor (MOS) transistor propagates to an output node via gate-drain capacitances CPD and CND at a timing of turning off a MOS transistor. Specifically, when the PMOS transistor is turned off, the PMOS transistor increases the output voltage VOUT by ΔV1.ΔV1=CPD/(COUT+CPD)×VDD  (1)
Further, when the NMOS transistor is turned off, the NMOS transistor decreases the output voltage VOUT by ΔV2.ΔV2=CND/(COUT+CND)×VDD  (2)
In addition, the charge injection is a phenomenon in which charges accumulated while a MOS transistor is in an on state in a gate-substrate (back gate) capacitance CPB of the MOS transistor affect an output voltage VOUT when the MOS transistor is turned off.
While the PMOS transistor is in an on state, charges QP≈CPB×(VDD−VTP) are stored between the gate and the substrate. VTP is a threshold voltage. When the PMOS transistor is turned off, a part of the charges QP, which is represented by αP×QP (αP denotes a coefficient), moves to the capacitor COUT and as a result, the output voltage VOUT is increased by ΔV3.ΔV3=αP×QP/COUT=αP×CPB×(VDD−VTP)/COUT  (3)
A phenomenon reverse to the above phenomenon occurs in the NMOS transistor, and as a result, the output voltage VOUT is decreased by ΔV4.ΔV4=αN×QN/COUT=αN×CNB×(VDD−VTN)/COUT  (4)
The error ΔVOUT between the output voltage VOUT and the input voltage VIN illustrated in FIG. 2 is the sum of ΔV1 to ΔV4. As is apparent from the expressions (1) and (2), an influence of the clock feed-through can be reduced by reducing the gate-drain capacitances CPD and CND. Accordingly, the influence can be reduced by reducing a gate width W.
Further, as can be seen from the expressions (3) and (4), an influence of the charge injection can be reduced by reducing the gate-substrate capacitances CPB and CNB. Accordingly, the influence can be reduced by reducing the gate width W and a gate length L.
As a result of investigation on the CMOS switch, the present inventors have recognized the following problems.
The clocks CK and CKB input to the gates of the NMOS transistor and the PMOS transistor are generated by setting a power supply voltage VDD as the high level and a ground voltage VSS (0 V) as the low level. Therefore, fluctuation of the power supply voltage VDD is fluctuation of gate voltages of the NMOS transistor and the PMOS transistor.
As described above, in order to reduce the clock feed-through and the charge injection, it is necessary to minimize sizes of the NMOS transistor and the PMOS transistor. When the NMOS transistor and the PMOS transistor of the same size are compared, the NMOS transistor has higher driving capability (smaller on-resistance) due to difference in mobility therebetween. Further, the on-resistances of the NMOS transistor and the PMOS transistor depend on the gate voltage, that is, the power supply voltage VDD.
FIG. 3 is a diagram illustrating an on-resistance of a CMOS switch in related art, in which the sizes of the NMOS transistor and the PMOS transistor are minimized. A horizontal axis represents an input voltage and a vertical axis represents the on-resistance. As can be seen from FIG. 3, an on-resistance RON when the power supply voltage VDD is 2.8 V is twice or more an on-resistance RON when the power supply voltage VDD is 5 V. It is desirable that fluctuation of the on-resistance RON is small since the on-resistance RON affects a charging speed of the capacitor COUT and thus an operation speed of the circuit in the sample hold circuit of FIG. 1A.